Phil Storrs PC Hardware book

Inside the Pentium Classic Processor

The Pentium surpasses the 486 in speed and power by using internal 256-bit Data paths and Pipe-lined processing that lets operations in all components of the microprocessor happen at once. In addition instruction processing is split into dual arithmetic logic units.

• The Bus Interface Unit retrieves data and code from RAM, 64 bits at a time.
• The Bus Interface Unit sends code along one 64-bit path to the 8K Code Cache and sends data along another 64-bit path to the 8K Data Cache. The two Caches collect data and Code until other components request that Data and Code.
• The Branch Prediction Unit inspects the code in the Code Cache to determine which of the two Pipelines, or Data paths, can most efficiently carry each instruction.
• The Instruction Pre-fetch Buffer obtains new instructions in 256-bit bursts and the Instruction Decode Unit prepares the Code for execution.
• The Floating Point Unit calculates any non-integer math and puts the result in the Data Cache.
• Two Integer Arithmetic Logic Units simultaneously take two sequential instructions of up to 32 bits each from the Instruction Decode Unit.
• The instructions are executed using Data placed in the Execution Unit's Registers from the Data Cache.
• The Data Cache receives the results of the calculation. The Cache sends the results to the Bus Interface Unit, which in turn writes the results to RAM.

The evolution of the 8086 family of chips from CISC to RISC processors

The first hint of the incorporation of RISC technology into the 8086 family came about in 1989 with the integration of a FPU (Floating Point Unit (better known as the maths co-processor)), more hard wired instruction logic and pipe lining. The FPU was Intel's response to the superior floating point performance of RISC processors and the additional hard wired instruction logic reduced the processors reliance on micro code (the stuff that drives a CISC processor internally). The pipe lining and the reduced micro code enabled the 486 processor to process many of it's instructions at an effective rate of one instruction per clock cycle, compared to a dozen or more clock cycles required by the earlier 8086 family chips. RISC processors achieve the same result partly by using simpler instructions that require fewer clock cycles.

Cyrix adapted these techniques to its improved 386 chips and created hybrids like there 486SLC. Texas Instruments and IBM took the technology even further with IBM using a larger Cache and introducing clock doubling technology. Because the 486 processor has only one pipeline it's theoretical throughput limit is one instruction per clock cycle and so Intel provided the Pentium with two pipelines so it could handle two instructions simultaneously. This allows the Pentium to issue some instructions at a rate of greater than one per clock cycle.

The nature of CISC instructions makes multiple pipelines difficult to implement. RISC processors generally use fixed length instructions (usually 32 bits long) whereas CISC processors use variable length instructions ranging in length from 8 bits to 120 bits. This means a CISC processor must decode each instructions length before it fetches the next instruction. Overcoming these limitations of a CISC processor means the Pentium is really a Hybrid CISC/RISC processor.

Another limitations imposed by the CISC origins of the 8086 family is the shortage of registers. This family of processors has only eight General Purpose Registers (GPR) but the Cyrix M1 chip overcame this limit with 32 GPRs that are Dynamically Renamed, making it appear as there are only eight general purpose registers. As the development of the PowerPC chips advances and IBM and the rest of the consortium espouse the virtues of RISC technology we will see more and more RISC technology incorporated into future Pentium microprocessor chips.

Why call the Pentium a Pentium ?